The present invention relates to a digital phase lock loop (PLL) circuit operable at high speed and, more particularly, to a digital PLL circuit for use in a hard disk drive.
It is known to use a PLL circuit to read out data from a hard disk drive by regenerating clock pulses synchronized with the reproduced data. PLL circuits for achieving this purpose have conventionally been constructed in analog form. Referring to FIG. 1, a typical PLL circuit of this type would include a sync field detector 1, a reference oscillator 2, a phase comparator 3, an error amplifier 4, a low pass filter 5, a voltage controlled oscillator (VCO) 6, and an address mark detector 7. The VCO generates a clock pulse having a frequency and phase synchronized with the data. The comparator generates pulses corresponding to the difference in the relative position of the data and the VCO timing clock pulse. The output of the comparator represents the "error signal" for controlling the PLL loop. The error amplifier converts the TTL (transistor-transistor logic) pulses from the phase comparator into constant current pulses and isolates any logic noise that might be present in the phase comparator outputs. The low pass filter arranged between the error amplifier and the VCO serves to reject certain frequency components while passing others, so that the high frequency jitter caused by various magnetic recording phenomena can be averaged or rejected.
The sync field detector prevents the VCO from slewing to a high frequency and being locked to a harmonic of the basic read/write frequency for the disk data. More specifically, when data is written to a disk there are areas on the disk that will contain invalid high frequency bursts, or "write glitches" due to a WRITE GATE being asserted and negated, data being recorded with a slightly different phase, a write current of an improper value at the beginning or end of the WRITE GATE, or for some other reason. If the phase comparator 3 is permitted to control the PLL loop during periods of time when these "glitches" are present, the VCO may be caused to slew to a high frequency and the VCO may then become locked to a higher harmonic when the normal data subsequently returns. To prevent this, the sync field detector 1 first maintains the VCO frequency locked to a desired frequency by passing a reference signal of predetermined frequency from the reference clock generator 2, e.g., 10 MHz, to the phase comparator 3, and the data is only provided to the phase comparator 3 after a sync field is detected.
In a typical Winchester drive data format, a sync field is provided in the form of an all-zero pattern of a predetermined number of bits recorded in front of each of the ID FIELD and the DATA FIELD and an address mark is recorded after each sync field but before the ID field or data field. When the pattern of 16 zero bits is recognized by the field detecting means, the switch 9 will be changed to select the reproduced data for provision to the phase comparator 3. The address mark detector 7 then examines the output of the switch 9 and provides a reset signal to the field detecting means 8 if an address mark is not detected within some predetermined period of time. The search for the sync field will then begin over again. Assuming that the address mark is detected, the reproduced data continues to be selected for a predetermined period of time long enough to detect the ID or data information. In this way, the reproduced data is not selected to control the PLL during the gap periods between fields when the WRITE GATE is turned on and off.
A great deal of effort is required in the design of the type of PLL circuit illustrated in FIG. 1. If different types of drives are used or if the data rate changes, an excessive amount of calculation and experimentation is required to derive new filter constants. Even if a PLL design is copied from a recommended circuit, there is no guarantee that it will perform satisfactorily. There are a great many variations in components from different manufacturers and in PC board design. In addition, each PLL circuit must be verified for performance and must be adjusted during testing by a reasonably qualified technician.
Further disadvantages of the conventional PLL circuit are that the loop filter 5 is necessary to remove logic noise which may be present in the output of the phase comparator, and the RC or LC components of the VCO must be carefully selected and adjusted, and even so the VCO will be extremely sensitive to logic noise.
If all conditions are ideal, the analog PLL can be made to provide excellent performance equal to or exceeding the drive's specifications, but ideal conditions are obviously very difficult to achieve.